Efficient Moments Extraction from VLSI Interconnections
نویسنده
چکیده
The transmission behaviour of interconnections in integrated circuits can be modelled accurately by lumped networks if the number of R(L)C sections is large enough. In practice these sections can be extracted from the layout, using a Finite Element or a Boundary Element Method. The number of sections obtained this way is very large, demanding a node reduction technique prior to simulation. This paper presents a reduction technique that transforms each of these large R(L)C networks into a minimal admittance network between the terminals, and at the same time preserves the moments of each admittance exactly, up to any desired order. Any R(L)C network can be dealt with, including both capacitive as well as inductive coupling between lines. The technique presented uses the principle of Gaussian elimination and can efficiently be incorporated in layout-to-circuit extractors, using a scan-line approach. An algorithm based on the technique is implemented in the layout-to-circuit extractor Space. Detailed timinganalysis of the interconnections is possible, using the extracted moments in combinationwith Padé approximants.
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تاریخ انتشار 1995